Accuracy of Memory Reference Traces of Parallel Computations in Trace-Driven Simulation

For given input, the global trace generated by a parallel program in a shared memory mul-tiprocessing environment may change as the memory architecture and management policies change. Consequently, if trace-driven simulation is used, care must be taken to adjust the global trace to reeect the reference pattern that would result from program execution in the new environment. Since the addresses may change as the environment changes, traditional process traces are not suucient. We propose a method for ensuring that a correct global trace is generated in the new environment. This method involves a new characterization of a parallel program that identiies its address change points and address aaecting points. An extension of traditional process traces, called the intrinsic trace of each process, is developed. The intrinsic traces maximize the de-coupling of program execution from simulation by describing the address ow graph and path expressions of each process program. At each point where an address is issued, the trace-driven simulator uses the intrinsic traces and the sequence of loads and stores before the current cycle , to determine the next address. The mapping between load and store sequences and next addresses to issue, sometimes, requires partial program reexecution. Programs that do not require partial program reexecution are called graph-traceable. We initially assume sequential consistency and then discuss the extension to the case where sequential consistency is violated.